-- $Id: $
-- File name:   tb_EOP_DETECT.vhd
-- Created:     10/18/2010
-- Author:      Christopher Sakalis
-- Lab Section: 4
-- Version:     1.0  Initial Test Bench

library ieee;
--library gold_lib;   --UNCOMMENT if you're using a GOLD model
use ieee.std_logic_1164.all;
--use gold_lib.all;   --UNCOMMENT if you're using a GOLD model

entity tb_EOP_DETECT is
end tb_EOP_DETECT;

architecture TEST of tb_EOP_DETECT is

  function INT_TO_STD_LOGIC( X: INTEGER; NumBits: INTEGER )
     return STD_LOGIC_VECTOR is
    variable RES : STD_LOGIC_VECTOR(NumBits-1 downto 0);
    variable tmp : INTEGER;
  begin
    tmp := X;
    for i in 0 to NumBits-1 loop
      if (tmp mod 2)=1 then
        res(i) := '1';
      else
        res(i) := '0';
      end if;
      tmp := tmp/2;
    end loop;
    return res;
  end;

  component EOP_DETECT
    PORT(
         D_PLUS : in std_logic;
         D_MINUS : in std_logic;
         EOP : out std_logic
    );
  end component;

-- Insert signals Declarations here
  signal D_PLUS : std_logic;
  signal D_MINUS : std_logic;
  signal EOP : std_logic;

-- signal <name> : <type>;

begin
  DUT: EOP_DETECT port map(
                D_PLUS => D_PLUS,
                D_MINUS => D_MINUS,
                EOP => EOP
                );

--   GOLD: <GOLD_NAME> port map(<put mappings here>);

process

  begin

-- Insert TEST BENCH Code Here

--     D_PLUS <= 
--     D_MINUS <= 

     D_PLUS <= '0';
     D_MINUS <= '0';

     wait for 80 ns;
     D_PLUS <= '0';
     D_MINUS <= '1';

     wait for 80 ns;
     D_PLUS <= '1';
     D_MINUS <= '0';

     wait for 80 ns;
     D_PLUS <= '1';
     D_MINUS <= '1';

     wait for 80 ns;
     D_PLUS <= '0';
     D_MINUS <= '0';

     wait;

  end process;
end TEST;